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Results 21 - 30 of 47 for xilinx (0.42 sec)

  1. Ultra - 96v2 board hardware manager Issue - Pro...

    3 hardware manager through Xilinx JTAG cable, it stops the functionality...
    discuss.96boards.org/t/ultra-96v2-board-hardwar... Cache
    Registered: Tue Jul 02 13:35:21 GMT 2024
    - Last Modified: Fri Oct 09 05:25:35 GMT 2020
    - 10.4K bytes
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  2. Why the preloaded Linux is configurated with on...

    maybe Xilinx TLB do not supporting address...
    discuss.96boards.org/t/why-the-preloaded-linux-... Cache
    Registered: Wed Jul 03 10:46:28 GMT 2024
    - Last Modified: Tue Mar 12 09:20:30 GMT 2019
    - 13.7K bytes
    - Viewed (0)
  3. PCIe connection on ultra96 - Ultra96 - 96Boards...

    off-the-shelf hardware with Xilinx SoCs, you should take a look...
    discuss.96boards.org/t/pcie-connection-on-ultra... Cache
    Registered: Tue Jul 02 12:34:48 GMT 2024
    - Last Modified: Fri Dec 27 19:37:09 GMT 2019
    - 13.2K bytes
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  4. Raw Ubuntu support - Ultra96 - 96Boards Forum

    10:51pm #2 @fletch does avnet or xilinx have updated caffe/opencv guides...
    discuss.96boards.org/t/raw-ubuntu-support/6288 Cache
    Registered: Wed Jul 03 09:47:31 GMT 2024
    - Last Modified: Mon Oct 29 09:26:30 GMT 2018
    - 13K bytes
    - Viewed (0)
  5. Setting up Vivado project for ultra96 and flash...

    6:21pm #2 Do you have a Xilinx JTAG cable? I will write up...
    discuss.96boards.org/t/setting-up-vivado-projec... Cache
    Registered: Wed Jul 03 08:51:04 GMT 2024
    - Last Modified: Tue Jul 03 05:03:37 GMT 2018
    - 21K bytes
    - Viewed (0)
  6. PCIe and GbE extension boards - Ultra96 - 96Boa...

    3:26pm #2 The Xilinx MPSoC supports PCIe, but I...
    discuss.96boards.org/t/pcie-and-gbe-extension-b... Cache
    Registered: Wed Jul 03 09:28:52 GMT 2024
    - Last Modified: Mon Sep 24 15:26:50 GMT 2018
    - 13.3K bytes
    - Viewed (0)
  7. Clk pin for RTL on ultra96v2 - Ultra96 - 96Boar...

    with “GC” or “HDGC” in the Xilinx pin name attached to the expansion...
    discuss.96boards.org/t/clk-pin-for-rtl-on-ultra... Cache
    Registered: Wed Jul 03 01:15:29 GMT 2024
    - Last Modified: Wed Feb 10 01:43:07 GMT 2021
    - 24K bytes
    - Viewed (0)
  8. AXI Interrupt Controller won't enter handler - ...

    the example code provided by Xilinx and exhausted all online resources...
    discuss.96boards.org/t/axi-interrupt-controller... Cache
    Registered: Tue Jul 02 12:28:14 GMT 2024
    - Last Modified: Fri Dec 20 08:51:13 GMT 2019
    - 14.5K bytes
    - Viewed (0)
  9. The Vivado tool is not detecting ultra 96 bard ...

    see AMD Xilinx UG973 for instructions: https://www.xilinx.com/s...
    discuss.96boards.org/t/the-vivado-tool-is-not-d... Cache
    Registered: Wed Jul 03 01:12:54 GMT 2024
    - Last Modified: Fri Mar 03 16:26:54 GMT 2023
    - 20.5K bytes
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  10. Help with testing out flaky binary - Ultra96 - ...

    More details on the following Xilinx’s forum thread: https://fo...
    discuss.96boards.org/t/help-with-testing-out-fl... Cache
    Registered: Wed Jul 03 09:57:04 GMT 2024
    - Last Modified: Mon Nov 19 14:09:38 GMT 2018
    - 13.3K bytes
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