This is a cache of https://discuss.96boards.org/t/410c-android-on-chip-uart-cannot-function/381. It is a snapshot of the page at 2024-09-20T03:14:55.264+0000.
410C/<strong>android</strong> on-chip UART cannot function - DragonBoard410c - 96Boards Forum

410C/android on-chip UART cannot function

Products Support DragonBoard410c
#1

Hi,

i’m trying to use the on-chip BLSP1’s low speed UART where the kernel source default is the high speed. i can now see the HSL1 device under /dev directory, but tested with the CRO and found no output even if i use echo command to send out data.

The following code i modified,
apq8016-sbc.dtsi:

/ {
	aliases {
		serial0 = &amp;blsp1_uart1;
		serial1 = &amp;blsp1_uart2;
	};
};
...
&amp;blsp1_uart1 {
	status = &quot;ok&quot;;
};

&amp;blsp1_uart2 {
	status = &quot;ok&quot;;
	pinctrl-names = &quot;default&quot;;
	pinctrl-0 = &lt;&amp;uart_console_sleep&gt;;
};

msm8916.dtsi:

/*	blsp1_uart1: uart@78af000 {
		compatible = &quot;qcom,msm-hsuart-v14&quot;;
		reg = &lt;0x78af000 0x200&gt;,
		      &lt;0x7884000 0x23000&gt;;
		reg-names = &quot;core_mem&quot;, &quot;bam_mem&quot;;
		interrupt-names = &quot;core_irq&quot;, &quot;bam_irq&quot;, &quot;wakeup_irq&quot;;
		#address-cells = &lt;0&gt;;
		interrupt-parent = &lt;&amp;blsp1_uart1&gt;;
		interrupts = &lt;0 1 2&gt;;
		#interrupt-cells = &lt;1&gt;;
		interrupt-map-mask = &lt;0xffffffff&gt;;
		interrupt-map = &lt;0 &amp;intc 0 107 0
				1 &amp;intc 0 238 0
				2 &amp;msm_gpio 1 0&gt;;

		qcom,bam-tx-ep-pipe-index = &lt;0&gt;;
		qcom,bam-rx-ep-pipe-index = &lt;1&gt;;
		qcom,master-id = &lt;86&gt;;

		clocks = &lt;&amp;clock_gcc clk_gcc_blsp1_uart1_apps_clk&gt;,
			 &lt;&amp;clock_gcc clk_gcc_blsp1_ahb_clk&gt;;
		clock-names = &quot;core_clk&quot;, &quot;iface_clk&quot;;

		qcom,msm-bus,name = &quot;blsp1_uart1&quot;;
		qcom,msm-bus,num-cases = &lt;2&gt;;
		qcom,msm-bus,num-paths = &lt;1&gt;;
		qcom,msm-bus,vectors-KBps =
				&lt;86 512 0 0&gt;,
				&lt;86 512 500 800&gt;;
		pinctrl-names = &quot;sleep&quot;, &quot;default&quot;;
		pinctrl-0 = &lt;&amp;hsuart_sleep&gt;;
		pinctrl-1 = &lt;&amp;hsuart_active&gt;;
		status = &quot;disabled&quot;;
//	};
//	
//	blsp1_uart2: serial@78b0000 {
	};*/

	blsp1_uart1: serial@78b0000 {
		compatible = &quot;qcom,msm-lsuart-v14&quot;;
		reg = &lt;0x78b0000 0x200&gt;;
		interrupts = &lt;0 108 0&gt;;
		status = &quot;disabled&quot;;
		clocks = &lt;&amp;clock_gcc clk_gcc_blsp1_uart2_apps_clk&gt;,
			 &lt;&amp;clock_gcc clk_gcc_blsp1_ahb_clk&gt;;
		clock-names = &quot;core_clk&quot;, &quot;iface_clk&quot;;
	};

	blsp1_uart2: uart@78af000 {
		compatible = &quot;qcom,msm-lsuart-v14&quot;;
		reg = &lt;0x78af000 0x200&gt;;
		interrupts = &lt;0 107 0&gt;;
		status = &quot;disabled&quot;;
		clocks = &lt;&amp;clock_gcc clk_gcc_blsp1_uart1_apps_clk&gt;,
			&lt;&amp;clock_gcc clk_gcc_blsp1_ahb_clk&gt;;
		clock-names = &quot;core_clk&quot;, &quot;iface_clk&quot;;
	};

msm8916-pinctrl.dtsi:

		pmx-uartconsole {
			qcom,pins = &lt;&amp;gp 4&gt;, &lt;&amp;gp 5&gt;;
			qcom,num-grp-pins = &lt;2&gt;;
			qcom,pin-func = &lt;2&gt;;
			label = &quot;uart-console&quot;;

		uart_console_sleep: uart-console {
				drive-strength = &lt;2&gt;;
				bias-pull-down;
			};
		};

		blsp1_uart2 {
			qcom,pins = &lt;&amp;gp 0&gt;, &lt;&amp;gp 1&gt;;
			qcom,num-grp-pins = &lt;2&gt;;
			qcom,pin-func = &lt;2&gt;;
			label = &quot;uart-blsp-2&quot;;

			uart_blsp2_sleep: uart-blsp-2 {
				drive-strength = &lt;2&gt;;
				bias-pull-down;
			};
		};

/*		blsp1_uart1_active {
			qcom,pins = &lt;&amp;gp 0&gt;, &lt;&amp;gp 1&gt;, &lt;&amp;gp 2&gt;, &lt;&amp;gp 3&gt;;
			qcom,num-grp-pins = &lt;4&gt;;
			qcom,pin-func = &lt;2&gt;;
		        label = &quot;blsp1_uart1_active&quot;;

			hsuart_active: default {
				drive-strength = &lt;16&gt;;
				bias-disable;
			};
		};
*/
		blsp1_uart1_sleep {
			qcom,pins = &lt;&amp;gp 0&gt;, &lt;&amp;gp 1&gt;, &lt;&amp;gp 2&gt;, &lt;&amp;gp 3&gt;;
			qcom,num-grp-pins = &lt;4&gt;;
			qcom,pin-func = &lt;0&gt;;
		        label = &quot;blsp1_uart1_sleep&quot;;

			hsuart_sleep: sleep {
				drive-strength = &lt;2&gt;;
				bias-disable;
			};
		};
#2

Can you check the permissions on /dev/ttyHSL1? I think you will find it is owned by root, and only has root access permissions. You can’t echo to it from a non-root shell. Last time I had this problem I had to add
chmod 777 /dev/ttyHSL2
to the end of /etc/init.qcom.post_boot.sh to maintain access. even if you change the permissions on the file, it will revert to the root only access every time you reboot.

#3

@ljking How did you modify /etc/init.qcom.post_boot.sh? I got a failed to copy 'init.qcom.post_boot.sh' to '/etc/init.qcom.post_boot.sh': Read-only file system error when trying to do that.

#4

adb root; adb remount did the trick.